#-----------------------------
#files options
#----------------------------
TB_FILE 		:= ../../tb/*.sv
SRC_FILE 		:= ../../src/*.v
LIB_FILE		:= .
IP_FILE			:= .
WAVE_FILE 		:= tb_peripheral.fsdb
ALL_FILE		:= $(TB_FILE)				\
				   $(SRC_FILE)				\
				   $(LIB_FILE)				\
				   $(IP_FILE)
#------------------------------
#tool options
#------------------------------
define_flag		:=	FSDB AUTO_CHECK FPGA_SIM
define_flag		:=	$(addprefix +define+,$(define_flag))


VERDI_PATH = $(VERDI_HOME)



vcs_comile_flag := 	-full64	  -LDFLAGS -Wl,--no-as-needed -lca  -kdb   -timescale=1ns/1ps  -P  $(VERDI_PATH)/share/PLI/VCS/LINUX64/novas.tab  $(VERDI_PATH)/share/PLI/VCS/LINUX64/pli.a +vcs+lic+wait   -assert svaext  +lint=all,noVCDE,noNS 				\
					+systemverilogext+sv	\
					-debug_access+all		\
					-l vcs_compile.log		\
					-timescale=1ns/1ns		\
					$(define_flag)

verdi_run_flag	:=	-2012					\
					$(define_flag)

vcs:
	vcs $(vcs_comile_flag) 		\
	$(ALL_FILE) 								

run:
	./simv

vsim: vcs run

vd:
	verdi $(verdi_run_flag)		\
	$(ALL_FILE) 				\
	-ssf $(WAVE_FILE)			\
	&



verdi:
	verdi -elab simv.daidir/kdb &
	
